1. Field of the Invention
The present invention relates to an image pick-up apparatus such as electronic still camera and video camera including an image sensing element for producing an image signal.
2. Description of the Related Art
FIG. 1 is a block diagram showing a known image pick-up apparatus. The image pick-up apparatus comprises a DC power supply source 51, DC—DC converter 52, central processing nit (CPU) 53, timing generator (TG) 54, vertical driver (V) 55 and charge coupled device (CCD) 56. The DC power supply source 51 supplies a power supply voltage VDD having a given value to the CPU 53 and TG 54 via the DC—DC converter 52 as well as to the V driver 55 and CCD 56 by means of a switch 57. TG 54 supplies sub-pulse timing signal XSUB, transfer gate pulse timing signal XTG and transfer pulse timing signal for a vertical shift register to the V driver 55 under the control of CPU 53. In response to these timing signals, the V driver 55 supplies sub-pulse VSUB and vertical shift register transfer pulse V to CCD 56, and CCD operates under the control of these timing pulses.
Now it is assumed that CCD 56 is of a vertical overflow drain type, and the sub-pulse timing signal XSUB is a timing signal for generating the sub-pulse VSUB which serves to discharge electrostatic charge stored in a photodiode in a vertical direction, said photodiode constituting a light receiving element. The transfer gate pulse timing signal XTG serves to transfer electrostatic signal charges stored in the photodiodes of CCD 56 into the vertical shift register. The vertical shift register transfer pulse timing signal XV is a timing signal for transferring the signal charges in the vertical shift register into a horizontal shift register. A vertical shift register transfer pulse V is generated on the basis of these transfer gate pulse timing signal XTG and vertical shift register transfer pulse timing signal XV.
In the conventional image pick-up apparatus shown in FIG. 1, when a main switch SW is closed at an instant to (see FIG. 2A), at first CPU 53 is initialized and a given process is executed in accordance with a program stored in an internal ROM in CPU. Then, DC—DC converter 52 is actuated by CPU 53 and begins to supply a given power supply voltage VDD to CCD 53 and TG 54 from an instant t1 as shown in FIG. 2A. At this time, all power supply voltages including VDD are not applied to the V driver 55 and CCD 56 as illustrated in FIG. 2D.
Usually the V driver 55 is constructed such that the V driver is made active when signals supplied to various input terminals thereof are in a low logic level L. Therefore, in the condition that the power supply voltages are not applied to the V driver 55 and CCD 56, CPU 53 supplies a control signal STDBY having the lower logic level L to TG 54 to keep TG in a standby condition as shown in FIG. 2C, and therefore the timing signals XSUB and XV supplied from TG 54 to the V driver 55 are set to a non-active high level H as depicted in FIG. 2E.
After that, as illustrated in FIG. 2C, at an instant t2, the control signal STDBY supplied from TG 54 to the V drive 55 is changed from the logic low level L to the logic high level H. Then, an internal clock generator provided in TG 54 is actuated to produce an internal clock, after a given time period during which the oscillation of the internal clock has become stable, the switch 57 is closed at an instant t3 and the supply of the power supply voltages including VDD to the V driver 55 and CCD 56 is initiated at an instant t4 as depicted in FIG. 2D. After a given time period, a reset signal RST is changed from L to H to initialize internal logic circuits of TG 54 at an instant t5(see FIG. 2B). After that, TG 54 operates in a normal manner to supply the timing signals XSUB, XTG and XV to the V driver 55 as shown in FIG. 2E.
In the known image pick-up apparatus, during a time period A from t1 at which the power supply voltage VDD is applied to CPU 53 and TG 54 to t4 at which the V driver 55 and CCD 56 begin to operate normally after the application of the power supply voltage VDD (see FIG. 2E), the respective timing signals XSUB, XTG and XV having the non-active high level H are supplied from the TG 54 to the V driver 55. Then, a leak current ILEAK might flow from TG 54 into the V driver 55 by means of a diode D provided in a protection circuit, a pull-up resistor R and other circuit elements provided in TG 54 as shown in FIG. 3. This leak current ILEAK flowing into the V driver 55 might amount to a power supply current having a very large magnitude, and therefore an internal circuits of the V driver 55 might be affected by the leak current, and in an extreme case, the V driver might be broken.
In order to avoid such a problem of the leak current, one may consider to provide a buffer in an input stage of the V driver 55 utilizing the teachings disclosed in Japanese Patent Application Laid-open Publication Kokai Hei 3-195331. However, it is apparent that such a solution raises a cost of the image pick-up apparatus.